1. Technical Field
The present invention relates to an operational amplifier and, more particularly, to an operational amplifier for an output buffer and a signal processing circuit using the same.
2. Description of the Related Art
An operational amplifier (or op-amp for short) is a high-gain differential amplifier. Generally, an operational amplifier includes two input terminals, one inverting (−) and one noninverting (+), and the output of the amplifier is the difference between the “IN+” and “IN−” voltages multiplied by the gain of the amplifier.
FIG. 1 is a circuit diagram of a basic two-stage operational amplifier. Referring to FIG. 1, a two-stage operational amplifier 100 includes a differential amplifier 110 for differentially amplifying a differential pair of input signals IN+ and IN−, and a driver 120 for driving an output node N11 of the differential amplifier 110 according to a bias voltage Vbias and an output signal of the differential amplifier 110. An output load comprising a resistance component and a capacitance component is connected to the output node N11.
The differential amplifier 110 includes NMOS transistors Q1, Q2 and Q5 and PMOS transistors Q3 and Q4. The noninverted and inverted input signals IN+ and IN− are inputted to gates of the NMOS transistors Q1 and Q2, respectively. The PMOS transistors Q3 and Q4 in a current mirror configuration are connected to NMOS transistors Q1 and Q2, respectively. The bias voltage Vbias is applied to the gate of the NMOS transistor Q5.
The driver 120 includes a PMOS transistor Q6 connected to the output node N11 of the differential amplifier 110 to serve as a current source, and an NMOS transistor Q7 serving as a current sink. The PMOS transistor Q6 charges the output load connected to the output node N11, and the NMOS transistor Q7 discharges the output node N11 according to a bias voltage Vbias applied to its gate. For example, when the noninverted input signal IN+ is higher in voltage than the inverted input signal IN−, the voltage level at the output node N11 is lowered and the PMOS transistor Q6 charges the output load connected to the output node N11. When the noninverted input signal IN+ is lower in voltage than the inverted input signal IN−, the voltage level at the output node N11 is increased, which means the PMOS transistor Q6 is turned off and the output node N11 is discharged by the NMOS transistor Q7.
In the above-described operational amplifier 100, the driving capability of the PMOS transistor Q6 is sufficient for charging the output node N11, but the driving capability of the NMOS transistor Q7 for discharging the output node N11 is limited to the quiescent current (i.e., the current when no load is present).
FIG. 2 is a diagram illustrating, both, an input signal 210 inputted to the input terminal of the two-stage operational amplifier shown in FIG. 1, and an output signal 220 outputted through the output node thereof. Referring to FIG. 2, since the PMOS transistor Q6 is controlled by the output signal of the differential amplifier 110 at a rising edge of the input signal 210, the slew rate of the output signal 220 does not matter. Slew rate refers to the maximum rate of change of an amplifier's output signal with respect to its input signal. In essence, slew rate is a measure of an amplifier's ability to follow its input signal.
However, since the NMOS transistor Q7 is controlled by the constant bias voltage Vbias at a falling edge of the input signal 210, time is required to discharge the electric charge stored in the capacitor of the output load which is connected to the output node N11. Therefore, at the time when the output signal 220 falls, slew rate becomes small.
In conventional op-amps, to improve a driving capability of the NMOS transistor Q7, the quiescent current of the NMOS transistor Q7 must be increased. However when the quiescent current of the NMOS transistor Q7 is increased, the power dissipation through the output node N11 is higher than desirable.
In a liquid crystal display (LCD) source driver for driving pixels of an LCD panel where, for example, the number of output buffers corresponds to the number of horizontal pixels, it is undesirable to increase the quiescent current of the NMOS transistor Q7.